UNITED STATES
SECURITIES AND EXCHANGE COMMISSION
Washington, D.C. 20549
FORM 10-K
x ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934
For the fiscal year ended December 31, 2016 or
o TRANSITION REPORT UNDER SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934
For the transition period from to
Commission file number: 001-37850
ATOMERA INCORPORATED
(Exact name of registrant as specified in its charter)
750 University Avenue, Suite 280
Los Gatos, California 95032
(Address, including zip code, of registrant’s principal executive offices)
(408) 442-5248
(Registrant’s telephone number, including area code)
Securities registered pursuant to Section 12(b) of the Act:
None
Securities registered pursuant to Section 12(g) of the Act:
Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes o No x
Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or 15(d) of the Exchange Act. Yes o No x
Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the past 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes x No o
Indicate by check mark whether the registrant has submitted electronically and posted on its corporate Web site, if any, every Interactive Data File required to be submitted and posted pursuant to Rule 405 of Regulation S-T (§ 232.405 of this chapter) during the preceding 12 months (or for such shorter period that the registrant was required to submit and post such files). Yes x No o
Indicate by check mark if disclosure of delinquent filers in response to Item 405 of Regulation S-K is not contained herein, and will not be contained, to the best of the registrant’s knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. o
Indicate by check mark whether the registrant is a large accelerated filer, an accelerated filer, a non-accelerated filer or a smaller reporting company (as defined in Rule 12b-2 of the Act):
Indicate by check mark whether the registrant is a shell company (as defined in Rule 12b-2 of the Exchange Act) Yes o No x
State the aggregate market value of voting and non-voting common equity held by non-affiliates computed by reference to the price at which the common equity was last sold, or the average bid and asked price of such common equity, as of the last business day of the registrant’s most recently completed second fiscal quarter: $85,851,285. The registrant has elected to use September 30, 2016, which was the last business day of the registrant’s most recently completed third fiscal quarter, as the calculation date because on June 30, 2016 (the last business day of the registrant’s most recently completed second fiscal quarter), the registrant was a privately-held company and therefore the registrant is unable to calculate market value as of that date. Shares of the registrant’s common stock held by each executive officer, director and holder of 10% or more of the outstanding common stock (as determined based on public filings) have been excluded in that such persons may be deemed to be affiliates. This calculation does not reflect a determination that certain persons are affiliates of the registrant for any other purpose.
As of March 27, 2017, there were 12,104,737 shares of the registrant’s common stock outstanding.
DOCUMENTS INCORPORATED BY REFERENCE
The registrant intends to file a definitive proxy statement pursuant to Regulation 14A within 120 days after the end of the fiscal year ended December 31, 2016. Portions of such proxy statement are incorporated by reference into Part III of this Form 10-K.
TABLE OF CONTENTS
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NOTE REGARDING FORWARD-LOOKING STATEMENTS
This Annual Report on Form 10-K contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933, as amended, and Section 21E of the Securities Exchange Act of 1934, as amended, that are intended to be covered by the “safe harbor” created by those sections. The words “believe,” “may,” “will,” “potentially,” “estimate,” “continue,” “anticipate,” “intend,” “could,” “would,” “project,” “plan,” “expect” and similar expressions that convey uncertainty of future events or outcomes are intended to identify forward-looking statements. These forward-looking statements include, but are not limited to, statements concerning the following:
These forward-looking statements are subject to a number of risks, uncertainties and assumptions, including those described in “Risk Factors” and elsewhere in this Annual Report and our subsequently filed Quarterly Reports on Form 10-Q. Moreover, we operate in a very competitive and rapidly changing environment, and new risks emerge from time to time. It is not possible for us to predict all risks, nor can we assess the impact of all factors on our business or the extent to which any factor, or combination of factors, may cause actual results to differ materially from those contained in any forward-looking statements we may make. In light of these risks, uncertainties and assumptions, the forward-looking events and circumstances discussed in this Annual Report may not occur and actual results could differ materially and adversely from those anticipated or implied in our forward-looking statements.
You should not rely upon forward-looking statements as predictions of future events. Although we believe that the expectations reflected in our forward-looking statements are reasonable, we cannot guarantee that the future results, levels of activity, performance or events and circumstances described in the forward-looking statements will be achieved or occur. Moreover, neither we nor any other person assumes responsibility for the accuracy and completeness of the forward-looking statements. We undertake no obligation to update publicly any forward-looking statements for any reason after the date of this Annual Report to conform these statements to actual results or to changes in our expectations, except as required by law.
You should read this Annual Report and the documents that we reference in this Annual Report and have filed with the Securities and Exchange Commission as exhibits with the understanding that our actual future results, levels of activity, performance and events and circumstances may be materially different from what we expect.
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General
We are engaged in the business of developing, commercializing and licensing proprietary processes and technologies for the $350+ billion semiconductor industry. Our lead technology, named Mears Silicon Technology™, or MST®, is a thin film of reengineered silicon that can be applied as a transistor channel enhancement to complementary metal-oxide semiconductor, or CMOS, type transistors, the most widely used transistor type in the semiconductor industry. MST® is our proprietary and patent protected performance enhancement technology that we believe addresses a number of key engineering challenges facing the semiconductor industry. We believe that by incorporating MST®, transistors can be smaller, with increased speed, reliability and energy efficiency. In addition, since MST® is an additive and low cost technology, it can be deployed on an industrial scale, with machines commonly used in semiconductor manufacturing. We believe that MST® can be widely incorporated into the most common types of semiconductor products, including analog, logic, memory and optical integrated circuits.
We do not intend to design or manufacture integrated circuits directly. Instead, we intend to develop and license technologies and processes that will offer the designers and manufacturers of integrated circuits a low-cost solution to the industry need for greater performance and lower power consumption.
In the mid-1980s, our founder, Dr. Robert Mears, was part of a team that re-engineered silica optical fiber to invent the erbium-doped fiber amplifier, or EDFA, a technology that increased the bandwidth of optical fiber more than 1,000 times. The invention of EDFA helped to revolutionize the development of broadband and to this day remains a key technology in the multi-hundred billion dollar optical communications industry. Dr. Mears anticipated scaling problems for silicon semiconductors and founded Atomera Incorporated in order to address those problems for the semiconductor industry.
Over the last 11 years, we have undertaken significant laboratory testing and engaged with a range of semiconductor industry and academic technology leaders to evaluate the effects of MST® on the performance of test chips in industrial fabrication environments. We believe this testing has demonstrated that MST® offers performance benefits, including increased speed, reliability and energy efficiency, beyond and in most cases additive to those provided by semiconductor performance enhancement technologies that are already widely used, such as dual stress liners and source/drain channel stressors, including eSiGe/eSiC, and can be implemented without significant additional cost or significant modification to the current semiconductor fabrication process.
We are now in the process of transitioning our MST® toward commercial adoption. Our intended initial customers are integrated device manufacturers, or IDMs, and foundries. During the evaluation phase of their engagement with us, potential customers test and evaluate the incorporation of our MST® technology into the integrated circuits they produce. As of the date of this Annual Report, we are in evaluations with two leading integrated device manufacturers, or IDMs, and one foundry. We are also collaborating with manufacturers of semiconductor fabrication equipment and developers of modeling tools. These parties are part of a semiconductor infrastructure supporting the industry with capital equipment for transistor production and transistor process modeling software, and we are in discussions with certain equipment manufacturers and tool developers concerning their incorporation of our MST® technology into the equipment and tools they offer to the industry. We are also marketing our MST® technology to fabless semiconductor manufacturers concerning their incorporation of MST® into the integrated circuits they design.
Atomera is currently focused on the CMOS semiconductor market due to the large opportunity it presents. However, we believe that the technologies underlying MST® are part of a larger platform of reengineered materials that have potential applications beyond CMOS, including:
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Industry Overview
Semiconductors, Generally
Recent years have seen a remarkable proliferation of consumer and commercial products, especially in wireless, automotive and mobile electronic devices. The growth of the Internet and cloud computing has provided people with new ways to create, store and share information. At the same time, the increasing use of electronics in cars, buildings, appliances and other consumer products is creating a broad landscape of “smart” devices and the evolution of wearable technologies and The Internet of Things.
These developments depend, in large part, on integrated circuits, or microchips, which are sets of electronic circuits on a single chip of semiconductor material, normally silicon. It is common for a single semiconductor chip to combine many components (processor, communications, memory, custom logic, input/output) resulting in highly complex chip designs. Transistors are the building blocks of integrated circuits and the most complex semiconductor chips today contain more than a billion transistors, each of which may have features that are much less than 1/1,000th the diameter of a human hair.
The most widely used transistors in semiconductor chips today are based on the CMOS technology. Among its many attributes, CMOS allows for a higher density of transistors on a chip and lower power usage than non-CMOS technologies.
The Pursuit of Increased Semiconductor Performance
For years, the semiconductor industry was able to almost double the number of transistors it could pack into a single microchip about every two years, a rate of improvement commonly known as “Moore’s Law.” The semiconductor industry uses the term “node” to describe the minimum line width or geometry on a semiconductor chip, expressed in nanometers (nm) for today’s technologies. Historically, the smaller the node, the smaller the transistors and the more closely they are packed together, producing chips that are denser and thus less costly on a per-transistor basis. Frequently, smaller nodes also correspond to an improvement in chip performance, making them the mile markers of Moore’s Law, with each node marking a new generation of chip-manufacturing technology.
Until recently, the industry succeeded at maintaining the rate of improvement predicted by Moore’s Law by scaling the key transistor parameters, such as shrinking feature sizes and operating voltages, thereby allowing more transistors to be packed onto a single microchip. This trend was facilitated in large part by the development of the CMOS technologies. However, a discontinuity in the rate of improvement delivered by scaling appeared a few years ago when transistor technology reached feature sizes below 100 nanometers. The industry responded with advanced materials to supplement the ongoing geometry shrinks. Some of those materials advances included strained silicon, Silicon on Insulator and High-K/Metal Gate.
In addition, due to the popularity of mobile devices and other electronic products, there is increasing demand for integrated circuits and systems with greater functionality and performance, reduced size, and much less power consumption as key requirements.
The designers and manufacturers of integrated circuits and systems — our potential customers — are facing intense pressure to deliver innovative products at ever shorter times-to-market, as well as at lower prices. In other words, innovation in chip and system design today often hinges on “better, sooner and cheaper.” We believe that the semiconductor industry has accepted that moving forward in the nano-era will require adoption of new innovations that extend the scaling formula, including those based on the use of new engineered materials, a market opportunity our MST® technology seeks to address. Because shrinking geometries at the smaller nodes incurs higher capital and manufacturing costs, only limited products can take on the increased cost burden and still be economically viable. We believe cost sensitive devices will turn to engineered materials, like MST®, to solve this problem.
Vertical Disaggregation of the Industry
In trying to keep research and development costs manageable, while attempting to satisfy the demand for increasingly complex semiconductors, certain designers and manufacturers of integrated circuits have transitioned to an open innovation model in which competing companies and third-party providers actively collaborate to address performance issues through various alliances, joint ventures, and licensing of externally developed technology.
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Historically, most semiconductor companies were vertically integrated. They designed, fabricated, packaged and tested their semiconductors using internally developed software design tools and manufacturing processes and equipment. As the cost and skills required for designing and manufacturing complex semiconductors have increased, the semiconductor industry has become disaggregated, with companies concentrating on one or more individual stages of the semiconductor development and production process. This disaggregation has fueled the growth of fabless semiconductor companies, design tool vendors, semiconductor equipment manufacturers, third-party semiconductor manufacturers (or foundries), semiconductor assembly, package and test companies, and intellectual property companies that develop and license technology to others.
While specialization has enabled greater development and manufacturing efficiency, it has also created an opportunity for IP-based companies, such as Atomera, that develop and license technology to meet fundamental, industry-wide challenges. These intellectual property companies have been able to gain broad adoption of their technology throughout the industry by working with companies within the semiconductor supply chain to evaluate and integrate their technology. Manufacturers and designers of semiconductors increasingly find it more cost-effective to license technologies from IP-based companies than internally developing processes that are not their core competence. Industry participants often will share a portion of the large up-front development cost of these technologies in exchange for a lower licensing fee or royalty rate. We believe this collaboration and integration benefits semiconductor companies by enabling them to bring new technology to market faster and more cost-effectively.